1. Field of the Invention
The present invention relates to a semiconductor device having a resetting circuit.
2. Description of the Related Art
Generally, a semiconductor device, such as a DRAM, includes a resetting circuit. When the power supply is turned on, the resetting circuit is operated to initialize an internal circuit, so that the semiconductor device is prevented from malfunctioning.
FIG. 1 shows an example of the resetting circuit implemented in the semiconductor device.
The resetting circuit has an nMOS transistor 2, a voltage generating circuit 4, a load circuit 6, and a waveform shaping circuit 8. The nMOS transistor connects a gate electrode to a node ND01, connects a drain electrode to a node ND02, and connects a source electrode to a ground line VSS. The voltage generating circuit 4 is formed such that resistors R1 and R2 are connected in series with each other with the node ND01 between a power supply line VCC and the ground line VSS. The load circuit 6 is formed such that an end of the load circuit 6 is connected to the power supply line VCC, and the other end of the load circuit 6 is connected to a resistor R3 connected to the node ND02. The waveform shaping circuit 8 has two inverters that are connected in series. In the waveform shaping circuit 8, its input is connected to the node ND02, and a reset signal RST is output from its output.
This type of resetting circuit detects that a supply voltage VCC has risen to a predetermined value by utilizing the threshold voltage of a transistor (in this example, the nMOS transistor 2), and inactivates the reset signal RST.
FIG. 2 shows the operation of the resetting circuit mentioned above. When an external supply voltage VCC starts to be supplied to the semiconductor device, the level of the reset signal RST rises in accordance with the external supply voltage VCC for a predetermined period of time, and then becomes low (inactivated). After the supply voltage VCC reaches a predetermined value, the internal circuit that needs to be initialized in the semiconductor device is initialized during a period T1 during which the reset signal RST is inactivated. When the reset signal RST is inactivated, the reset operation is completed, so:that the internal circuit begins to perform a normal operation.
Recently, the operating voltage of semiconductor devices has become low, and, accordingly, a supply voltage VCC supplied from external sources has become low. The ratio of the threshold voltage of a transistor to the supply voltage VCC is high since the threshold voltage of the transistor has almost no dependence on the supply voltage VCC. As a result, the detection level of the supply voltage VCC of the resetting circuit greatly varies depending on a change in the threshold voltage, and the amount (T2 in FIG. 2) of deviation in the inactivation timing of the reset signal RST with respect to a change in the threshold voltage becomes larger than that in the case where the operating voltage is high. The threshold voltage of the transistor varies with the manufacturing conditions, the position of a chip on a wafer, and the position of the wafer in a production lot, of the semiconductor device, or depends on the temperature when the semiconductor device is operating.
For example, a reset period T1 is shortened if the inactivation timing of the reset signal RST deviates to an early-timing side. This case raises a fear that the internal circuit will not be normally initialized. In the worst case, a high-level period of the reset signal RST necessary to initialize the internal circuit will disappear. On the other hand, if the inactivation timing of the reset signal RST deviates to a late-timing side, there is a fear that the reset signal RST will not be inactivated (i.e., be always at a high level).
There is a case in which, for example, the aforementioned voltage generating circuit 4 is formed of many resistors and fuses, in order to deal with the deviation of the threshold voltage of the transistor at the time a semiconductor device is manufactured. In this case, some of the resistors to be connected in series are selected by trimming the fuses, and a voltage generated in the node ND01 is adjusted according to a threshold voltage. However, the thus constructed voltage generating circuit has a disadvantage in that the chip size increases because a large layout area is required for the resistors and the fuses. Additionally, manufacturing costs increase because a step to trim the fuses is required.
An object of the present invention is to generate a reset signal which is not influenced by a change in the threshold voltage of a transistor. In other words, the object is to reduce fluctuations in the inactivation timings of reset signals generated by a resetting circuit.
Another object of the present invention is to reliably initialize an internal circuit of a semiconductor device by the reset signal, and thereby prevent malfunctioning of the semiconductor device.
According to one of the aspects of the present invention, the resetting circuit includes a first transistor that receives a first voltage at a gate electrode and a second transistor that receives a second voltage at the gate electrode. The second transistor is formed such that the ratio W/L (transistor size) of a gate width W to a channel length L is larger than the ratio W/L of the first transistor. The first voltage rises in accordance with the rise of a supply voltage. The second voltage rises in accordance with the rise of the supply voltage, and is lower than the first voltage.
The gate voltage (accurately, gate-to-source voltage) of the second transistor is always lower than the gate voltage of the first transistor. The transistor size of the second transistor is larger than that of the first transistor. Therefore, the drain-to-source current (i.e., subthreshold current) of the second transistor is larger than the drain-to-source current of the first transistor for a while after the supply voltage is applied (i.e., while the supply voltage is low).
Since the first voltage is always higher than the second voltage, an increase in the drain-to-source current of the first transistor is larger than an increase in the drain-to-source current of the second transistor. In other words, an inversion layer is formed in the first transistor earlier than in the second transistor. As a result, the drain-to-source current of the first transistor is equalized with the drain-to-source current of the second transistor at a predetermined supply voltage, and thereafter the drain-to-source current of the first transistor becomes larger than that of the second transistor. That is, an inversion occurs between the drain-to-source currents of the first and second transistors by the predetermined supply voltage.
If the threshold voltages of the first and second transistors are both high, both the drain-to-source currents thereof become large. Therefore, the supply voltage in which the electric current is inverted is substantially the same as when the threshold voltage is at its average level. The same applies to the case in which the threshold voltages of the first and second transistors are both low. That is, the supply voltage in which the electric current is inverted is substantially the same as when the threshold voltage is at its average level. Since the control circuit generates the reset signal when the values of the drain-to-source currents cross, the reset signal can always be generated at the predetermined supply voltage, independent from the threshold voltage of the transistor.
Therefore, in the case when the resetting circuit is formed in a semiconductor device, an internal circuit of the semiconductor device is initialized whenever the supply voltage reaches a predetermined value, without being influenced by a change in the threshold voltage. the reset signal may be generated by, for example, the direct detection of a current value, and may be generated by utilizing a voltage generated in the drain electrode of the transistor.
According to another aspect of the resetting circuit in the present invention, since the channel lengths L of the first and second transistors are equalized with each other, the two transistors maintain predetermined relative relations with each parameter in subthreshold characteristic during changes in each of the parameters. This results in a desired V-l characteristic to be easily realized.
According to still another aspect of the resetting circuit in the present invention, the resetting circuit includes a load circuit. The load circuit is connected to the drain electrode of the first transistor and to the drain electrode of the second transistor, and supplies an electric current to the first transistor and the second transistor. The reset signal is generated in accordance with a change in voltages of at least one of the drain electrode of the first transistor and the drain electrode of the second transistor. That is, the reset signal can easily be generated by generating a voltage based on the drain-to-source currents of the first and second transistors by the load circuit. A predetermined circuit can reliably be initialized by the reset signal generated in response to a change in the voltage.
According to still another aspect of the resetting circuit in the present invention, the resetting circuit includes an earth circuit. The earth circuit is connected to the source electrode of the first transistor and to the source electrode of the second transistor, and adjusts an electric current running through the first and second transistors. Therefore, the reset signal can be generated with minimum electric current consumed by the resetting circuit.
According to still another aspect of the resetting circuit in the present invention, the first voltage and the second voltage are reliably generated by a voltage generating circuit.